Computer Organization Principles Review Summary (Part 6) Bus System

Chapter 6: Bus System#

6.1 Concept and Structure of the Bus#

6.1.1 Basic Concept of the Bus (Key Points)#

A digital computer is composed of several functional components, which work together to form a complete computer system.

Definition of the Bus#

  • It is not possible for the various functional components of a computer to be fully interconnected, so there is a need for a common information channel, which is the bus.

  • The bus is the interconnection mechanism that constitutes the computer system, and it is the common path for data transfer between multiple functional components of the system. With the help of the bus connection, the computer exchanges address, data, and control information between various functional components and works based on resource contention.
    The bus can be divided into the following categories:

  • Internal bus: The bus that connects various registers and arithmetic units within the CPU.

  • System bus: External bus. The bus that connects the CPU and other high-speed functional components in the computer system.

  • I/O bus: The bus that connects low-speed I/O devices to each other.

Characteristics of the Bus#

The characteristics of the bus can be divided into: physical characteristics, functional characteristics, electrical characteristics, and timing characteristics.

  • Physical characteristics: The physical connection method of the bus (number, plug, socket shape, pin arrangement method).
  • Functional characteristics: The function of each line.
  • Electrical characteristics: The transmission direction and valid voltage range of the signal on each line.
  • Timing characteristics: Specifies when each bus is valid.

Standardization of the Bus#

  • For the interchangeability of function components produced by different manufacturers, it is necessary to standardize the system bus. Currently, there are many bus standards, such as PCI, ISA, etc.
  • Advantages of using a standard bus:
    • Simplifies system design and structure, improves system reliability.
    • Facilitates system expansion and updates.

Bus Bandwidth#

The maximum transfer rate that the bus itself can achieve.
Unit: megabytes per second (MB/s)

  • The number of data bits that can be transferred in one operation.
  • For example, S100 is 8 bits, ISA is 16 bits, EISA is 32 bits, and PCI-2 can reach 64 bits.
  • The bus width will not exceed the width of the microprocessor's external data bus.

【Example 1】(1) A bus transfers 4 bytes of data in one bus cycle. Assuming that one bus cycle is equal to one bus clock cycle, and the bus clock frequency is 33MHz, what is the bus bandwidth?
(2) If a bus transfers 64-bit data in one bus cycle, and the bus clock frequency is increased to 66MHz, what is the bus bandwidth?

Solution: (1) Let Dr represent the bus bandwidth, T represent the bus clock cycle, and D represent the amount of data transferred in one bus cycle.
According to the definition, Dr = D / T = D × (1 / T) = D × f = 4B × 33 × 106/s = 132MB/s
(2) 64 bits = 8B
Dr = D × f = 8B × 66 × 106/s = 528MB/s

6.1.2 Connection Methods of the Bus#

  • There are various types of peripheral devices with different speeds, and it is not possible to simply connect the peripheral devices to the CPU.
  • Adapter (interface): It achieves the matching and synchronization of working speeds between high-speed CPUs and low-speed peripherals, and completes all data transfer and control between the computer and peripherals.
  • Most buses are constructed in the same way, with differences in the width of data lines and address lines and the number and function of control lines.
  • Two basic types of bus structures in a standalone system:
    • Single bus: Uses a single system bus to connect the CPU, memory, and I/O devices.
      • Features: In a single bus structure, the logic components connected to the bus are required to operate at high speed so that they can quickly obtain bus control when some devices need to use the bus; and when the bus is no longer used, they can quickly relinquish bus control.
      • Otherwise, due to the shared use of a single bus by multiple functional components, it may cause significant time delays.Single Bus Structure
    • Multiple buses: Multiple buses are used to interconnect the CPU, main memory, and I/O devices. As shown in the figure.
      • High-speed CPU bus: Used between the CPU and cache.
      • System bus: Main memory is connected to it. High-speed buses can be connected to high-speed LAN (100Mb/s local area network), video interfaces, graphics interfaces, SCSI interfaces (support local disk drives and other peripherals), and Firewire interfaces (support high-capacity I/O devices). The high-speed bus is connected to the expansion bus through an expansion bus interface, and the expansion bus can connect I/O devices that operate in serial mode.
      • The CPU bus, system bus, and high-speed bus are interconnected through bridges. Bridges are essentially logical circuits with buffering, conversion, and control functions.
      • The multiple bus structure reflects the connection of high-speed, medium-speed, and low-speed devices to different buses for simultaneous operation, in order to improve the efficiency and throughput of the bus, and changes in the processor structure do not affect the high-speed bus.Multiple Bus Structure
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